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Effect of interlayer trapping and detrapping on the determination of interface state densities on high-k dielectric stacks

机译:层间俘获和去俘获对高k电介质堆栈界面态密度测定的影响

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摘要

Al/HfO(2)/SiNx:H/n-Si metal-insulator-semiconductor (MIS) capacitors have been studied by electrical characterization. Films of silicon nitride were directly grown on n-type silicon substrates by electron-cyclotron-resonance assisted chemical-vapor-deposition (ECR-CVD). Silicon nitride thickness was varied from 2.96 to 6.64 nm. Afterwards, 12 nm thick hafnium oxide films were deposited by the high-pressure reactive sputtering (HPS) approach. Interface state densities were determined by deep-level transient spectroscopy and simultaneous high and low frequency capacitance-voltage (HLCV). The simultaneous measurements of the high and low frequency capacitance voltage provide interface trap density values in the range of 10(11) cm(2) eV(-1) for all the samples. However, a significant increase of this density of about two orders of magnitude was obtained by DLTS for the thinnest silicon nitride interfacial layers. In this work we probe that this increase is an artifact that must be attributed to traps existing at the HfO(2)/SiN(x):H interlayer interface. These traps are more easily charged or discharged as this interface comes near the substrate, that is, as thinner the SiN(x):H interface layer. The trapping/detrapping mechanisms increase the capacitance transient and, in consequence, the DLTS measurements have contributions not only from the insulator/substrate interface but also from the HfO(2)/SiN(x):H interlayer interface.
机译:通过电气特性研究了Al / HfO(2)/ SiNx:H / n-Si金属绝缘体半导体(MIS)电容器。通过电子回旋共振辅助化学气相沉积(ECR-CVD)在n型硅衬底上直接生长氮化硅膜。氮化硅厚度在2.96至6.64nm之间变化。之后,通过高压反应溅射(HPS)方法沉积12 nm厚的氧化f膜。界面状态密度由深层瞬态光谱法和同时的高频和低频电容电压(HLCV)确定。同时测量高频和低频电容电压可为所有样品提供10(11)cm(2)eV(-1)范围内的界面陷阱密度值。然而,对于最薄的氮化硅界面层,通过DLTS获得了大约两个数量级的该密度的显着增加。在这项工作中,我们探究到这种增加是一种伪影,必须将其归因于HfO(2)/ SiN(x):H层间界面处存在的陷阱。随着该界面靠近基板,即SiN(x):H界面层越薄,这些陷阱越容易充电或放电。俘获/去俘获机制增加了电容瞬变,因此,DLTS测量不仅对绝缘体/基板界面有贡献,而且对HfO(2)/ SiN(x):H夹层界面也有贡献。

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